System and method for generating a field effect transistor corner model

ABSTRACT

Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value with all statistical model parameters set at their nominal values. Then, multiple additional simulation runs are performed to determine corner performance values. In each successive additional simulation run, statistical model parameters of the different types of field effect transistors are offset from their nominal model parameters values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined.

BACKGROUND

The system and method disclosed herein relate to generating a field effect transistor (FET) corner model and, more particularly, to generating a FET corner model that preserves the partial correlations between statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of FETs within an integrated circuit.

Typically, partial correlations exist between certain statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of field effect transistors (e.g., a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), a regular threshold voltage p-type field effect transistor (RVT pFET), a high threshold voltage n-type field effect transistor (HVT nFET), a high threshold voltage p-type field effect transistor (HVT pFET), etc.) with regard to performance (e.g., delay of logic gates) within the same integrated circuit. Those skilled in the art will recognize that a “partial correlation” is a measurable degree of association between two otherwise random variables. It would be advantageous to be able to generate a FET corner model that accurately preserves these partial correlations without requiring a significant number (e.g., hundreds, thousands or tens of thousands) of simulations.

SUMMARY

In view of the foregoing, disclosed herein are a system, method and computer program product for generating a field effect transistor (FET) corner model for a given performance target (e.g., delay of logic gates) that accurately preserves partial correlations between corresponding statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value (e.g., a nominal delay value) with all statistical model parameter values of the field effect transistors set at their nominal model parameter values (e.g., nominal channel length values, nominal threshold voltage values, nominal overlap capacitance values, nominal channel widths, etc.). Then, multiple additional simulation runs are performed to determine corner performance values (e.g., corner delay values). In each successive additional simulation run, the statistical model parameters of the different types of field effect transistors are properly set at different model parameter values (e.g., different channel length values, different threshold voltage values, different overlap capacitance values, different channel widths, etc.) that are offset from their nominal model parameters values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined. This technique preserves the partial correlations between the statistical model parameters of the different types of field effect transistors and does so without requiring the performance of a large number of simulations and without requiring knowledge of the sensitivities of the performance target.

More particularly, disclosed herein is a computer system for modeling integrated circuit performance. This computer system can comprise a memory and at least one processor.

The memory can store a design for an integrated circuit. This integrated circuit can comprise at least two different types of field effect transistors. For example, the integrated circuit can comprise any two or more of the following: a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), a regular threshold voltage p-type field effect transistor (RVT pFET), a high threshold voltage n-type field effect transistor (HVT nFET), a high threshold voltage p-type field effect transistor (HVT pFET), etc.

The processor(s) can access the design in the memory and can generate a corner model for a performance target that preserves partial correlations between corresponding statistical model parameters of the different types of field effect transistors. The performance target can comprise, for example, delay of logic gates. The corresponding statistical model parameters can comprise, for example, channel lengths, threshold voltages, overlap capacitances or channel widths.

To accomplish this, the processor(s) can perform an initial simulation run to determine a nominal performance value. During the initial simulation run, the values of the corresponding statistical model parameters (e.g., the channel length values, the threshold voltage values, the overlap capacitance values, or channel width values) of the two or more different types of field effect transistors can be set at their respective nominal model parameter values (e.g., nominal channel length values, nominal threshold voltage values, nominal overlap capacitance values, or nominal channel width values, respectively). The processor(s) can further perform multiple additional simulation runs to determine corner performance values. During each successive additional simulation run, the values of the corresponding statistical model parameters (e.g., the channel length values, the threshold voltage values, the overlap capacitance values or the channel width values) of the two or more different types of field effect transistors can be set at different model parameter values that are offset from their respective nominal model parameters values in correlated ways.

Once the simulation runs are preformed as described above, the processor(s) can determine a standard deviation for the performance target based on performance differences between each of the corner performance values and the nominal performance value.

For example, in the system described above, an initial simulation run can be performed by the processor(s) to determine a nominal delay value of the logic gates. During the initial simulation run, the corresponding channel length values of the two or more different types of field effect transistors can be set at their respective nominal channel length values. Next, multiple additional simulation runs can be performed by the processor(s) to determine corner delay values. During each successive additional simulation run, the corresponding channel length values of the two or more different types of field effect transistors can be set at different channel length values that are offset from their respective nominal channel length values in correlated ways. Once the simulation runs are preformed, the processor(s) can determine a standard deviation for the delay value based on delay differences between each of the corner delay values and the nominal delay value.

Also disclosed herein is a computer-implemented method for modeling integrated circuit performance.

The method can comprise accessing, from a memory accessible by a computer system, a design for an integrated circuit. This integrated circuit can comprise at least two different types of field effect transistors. For example, the integrated circuit can comprise any two or more of the following: a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), a regular threshold voltage p-type field effect transistor (RVT pFET), a high threshold voltage n-type field effect transistor (HVT nFET), a high threshold voltage p-type field effect transistor (HVT pFET), etc.

The method can further comprise generating, by the computer system, a corner model for a performance target that preserves partial correlations between corresponding statistical model parameters of the different types of field effect transistors. The performance target can comprise, for example, delay of logic gates. The corresponding statistical model parameters can comprise, for example, channel lengths, threshold voltages, overlap capacitances, or channel widths.

To accomplish this, an initial simulation run can be performed to determine a nominal performance value. During the initial simulation run, the values of the corresponding statistical model parameters of the two or more different types of field effect transistors can be set at their respective nominal model parameter values. The multiple additional simulation runs can be performed to determine corner performance values. During each successive additional simulation run, the values of the corresponding statistical model parameters of the two or more different types of field effect transistors can be set at different model parameter values that are offset from their respective nominal model parameters values in correlated ways.

Once the simulation runs are preformed as described above, a standard deviation for the performance target can be determined based on performance differences between each of the corner performance values and the nominal performance value.

For example, in the method described above, an initial simulation run can be performed to determine a nominal delay value. During the initial simulation run, the corresponding channel length values of the two or more different types of field effect transistors can be set at their respective nominal channel length values. Next, multiple additional simulation runs can be performed to determine corner delay values. During each successive additional simulation run, the corresponding channel length values of the two or more different types of field effect transistors can be set at different channel length values that are offset from their respective nominal channel length values in correlated ways. Once the simulation runs are preformed, a standard deviation for the delay value can be determined based on delay differences between each of the corner delay values and the nominal delay value.

Also disclosed herein are embodiments of a computer program product. This computer program product can comprise a computer readable storage medium, which stores computer program code. The computer program code can be executable by a computer to perform the above-described method.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:

FIG. 1A is a nFET channel length (L_(nfet)) to pFET channel length (L_(pfet)) graph illustrating the accuracy of a prior art corner model when there is an absence of any correlation between the two channel length values;

FIG. 1B is another nFET channel length (L_(nfet)) to pFET channel length (L_(pfet)) graph illustrating the inaccuracy of a prior art corner model when there is a partial correlation between the two channel length values;

FIG. 2 is a schematic diagram illustrating a computer system for modeling integrated circuit performance and, particularly, for generating a field effect transistor (FET) corner model;

FIG. 3 is a schematic diagram illustrating an exemplary hardware environment for implementing systems, methods and computer program products disclosed herein;

FIG. 4 is a schematic diagram illustrating an exemplary complementary metal oxide semiconductor (CMOS) inverter for which a corner model can be generating using the systems, methods and computer program products disclosed herein;

FIG. 5 is a nFET channel length (L_(nfet)) to pFET channel length (L_(pfet)) graph illustrating the accuracy of the disclosed corner model generation technique when there is a partial correlation between the two channel length values;

FIG. 6 is an exemplary correlation matrix illustrating exemplary partial correlations that may exist between the channel lengths of four different types of FETs in an exemplary integrated circuit;

FIG. 7 is another exemplary correlation matrix illustrating exemplary partial correlations between the channel lengths of only two of four different types of FETs in a set of statistical models as shown in FIG. 6, when only those two FETs affect a performance target;

FIG. 8 is a flow diagram illustrating a method for modeling integrated circuit performance and, particularly, for generating a field effect transistor (FET) corner model; and

FIG. 9 is a flow diagram illustrating in greater detail the process 806 of FIG. 8.

DETAILED DESCRIPTION

As mentioned above, typically, partial correlations exist between certain statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of field effect transistors (e.g., a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), a regular threshold voltage p-type field effect transistor (RVT pFET), a high threshold voltage n-type field effect transistor (HVT nFET), a high threshold voltage p-type field effect transistor (HVT pFET), etc.) with regard to performance (e.g., delay of logic gates) within the same integrated circuit. Those skilled in the art will recognize that a “partial correlation” is a measurable degree of association between two otherwise random variables.

Techniques for generating a FET corner model typically (i) do not preserve these partial correlations, (ii) preserve them but require a significant number (e.g., hundreds, thousands or tens of thousands) of simulations in order to do so accurately, or (iii) preserve them but do not do so accurately. For illustration purposes, such techniques are described below with respect to an integrated circuit comprising a simple complementary metal oxide semiconductor (CMOS) inverter with an n-type field effect transistor (nFET) electrically connected in series to a p-type field effect transistor (pFET), a performance target comprising delay of the inverter and corresponding statistical model parameters with partial correlations comprising channel lengths.

For example, one technique for generating a FET corner model for such an integrated circuit involves determining a nominal performance value (e.g., a nominal delay value (τ_(nom))) by running a simulation with the channel lengths of the nFET and pFET set at their nominal model parameter values (i.e., at their nominal channel length values (L_(nfet,nom) and L_(pfet,nom))). A first corner delay value (τ₁) is then determined by running an additional simulation with the pFET channel length set at its nominal channel length value (L_(pfet,nom)) and the nFET channel length set at a corner channel length value (L_(nfet,nom)+ησ, where the parameter η can be +1, +2, +3, −1, −2, or −3, etc. Then, a second corner delay value (τ₂) is determined by running yet another additional simulation with the nFET channel length set at its nominal channel length value (L_(nfet,nom)) and the pFET channel length set at a corresponding corner channel length value (L_(pfet,nom)+ησ) (see FIG. 1A or FIG. 2A). Finally, the following expressions can be used to obtain the variance (σ_(τ,corner) ²) and standard deviation (σ_(τ,corner)) of the corner delay:

$\begin{matrix} {{{\sigma_{\tau,{corner}}^{2} = {\frac{1}{\eta^{2}}\left\lbrack {\left( {\tau_{1} - \tau_{nom}} \right)^{2} + \left( {\tau_{2} - \tau_{nom}} \right)^{2}} \right\rbrack}};}{{and},}} & \left( {1a} \right) \\ {\sigma_{\tau,{corner}} = {{\frac{1}{\eta}\left\lbrack {\left( {\tau_{1} - \tau_{nom}} \right)^{2} + \left( {\tau_{2} - \tau_{nom}} \right)^{2}} \right\rbrack}^{\frac{1}{2}}.}} & \left( {1b} \right) \end{matrix}$

Namely, the standard deviation of the corner delay (σ_(τ, corner)) is a root sum of squares (RSS) of the differences between corner delays and nominal delay. When there is no correlation between the channel length values of the nFET and pFET (i.e., when the correlation coefficient C_(nfet,pfet)=0, as illustrated by the plot of circle 101 a in the nFET channel length (L_(nfet)) to pFET channel length (L_(pfet)) graph of FIG. 1A), this method is accurate. On the other hand, when there is partial correlation between the channel length values of the nFET and pFET (i.e., when correlation coefficient C_(nfet,pfet)≠0, as illustrated by the plot of ellipse 101 b in the nFET channel length (L_(nfet)) to pFET channel length (L_(pfet)) graph of FIG. 1B), this technique generates results that do not preserve that partial correlation between the channel length values of the nFET and pFET such that the standard deviation determined using Eq. (1b) is inaccurate. This will be explained in the following.

A well-known technique for generating an accurate FET corner model for such an integrated circuit is to generate statistical models and use the statistical models to run Monte Carlo simulations. For example, for a pair of FET models, the channel length values of the nFET and pFET can be partially correlated as illustrated by the following set of statistical models generated for channel lengths: L _(nfet) =L _(nfet,nom)+σ(α₁₁ g ₁+α₁₂ g ₂)=L _(nfet,nom)+σ(a ₁ g ₁ +a ₂ g ₂),  (2a) L _(pfet) =L _(pfet,nom)+σ(α₂₁ g ₁+α₂₂ g ₂)=L _(pfet,nom)+σ(a ₁ g ₁ −a ₂ g ₂),  (2b) with a ₂=±√{square root over (1−a ₁ ²)},  (3) where each of g₁ and g₂ is an independent random variable of mean zero and standard deviation one, namely,

g ₁

=

g ₂

=0,

g ₁ ²

=

g ₂ ²

=1,

g ₁ g ₂

=0.

The value of the coefficient a₁ in the set of statistical models for channel lengths (2a)-(2b) varies with the correlation coefficient (C_(nfet,pfet)), which can be expressed as follows: a ₁ ² −a ₂ ²=2a ₁ ²−1=C _(nfet,pfet),  (4) and which can be simplified as follows: a ₁=±√{square root over ((1+C _(nfet,pfet))/2)},  (5)

Thus, for example, to achieve a C_(nfet,pfet)=0.28, the following must be true: a₁=0.8 and a₂=0.6. Assume the existence of a set of statistical models for the integrated circuit with all parameters and coefficients already known, the task is then finding a corner model given the set of statistical models.

Inverter delay is a function of two channel lengths. In the linear approximation (which holds when variations are small), the delay (τ) varies linearly with the variations of two channel lengths, τ=f(L _(nfet) ,L _(pfet))≈τ_(nom) +s ₁ ΔL _(nfet) +s ₂ ΔL _(pfet),  (6) where s₁ (s₂) is the sensitivity of the performance target (inverter delay here) with respect to the variation in nFET (pFET) channel length. The standard deviation of the performance target from Monte Carlo simulation can be obtained analytically in the following linear approximation, σ_(τ,MC) ²=

(τ−τ_(nom))²

=

(s ₁ ΔL _(nfet) +s ₂ ΔL _(pfet))²

=σ²(s ₁ ² +s ₂ ²+2s ₁ s ₂ C _(nfet,pfet)).  (7)

While the Monte-Carlo technique does provide an accurate standard deviation for the delay, it requires hundreds, thousands or tens of thousands of runs of simulations, which is both time consuming and CPU costly. Thus, there is a need to find a quick approach to obtain the standard deviation of the performance target. The corner/sensitivity method is such a method. The commonly used corner approach, however, does not produce the correct standard deviation of a performance target when there are partial correlations among the statistical model parameters of devices used. We will explain this in the following paragraphs.

Prior-art corner/sensitivity methods typically proceed as follows. A nominal delay value (τ_(nom)) is first determined by running a simulation with the channel lengths of both nFET and pFET set at their nominal values (i.e., at their nominal channel length values (L_(nfet,nom) and L_(pfet,nom))). Then, in a first additional simulation run, a first corner delay value (τ₁) is determined by setting pFET channel length at its nominal value (L_(pfet,nom)) but offsetting nFET channel length by a few standard deviation (ησ), i.e., ΔL_(nfet,1)=ησ and ΔL_(pfet,1)=0. In the linear approximation, the first corner delay value (τ₁) is given by Eq. (6), τ₁=τ_(nom) +s ₁ ΔL _(nfet,1) +s ₂ ΔL _(pfet,1)=τ_(nom) +s ₁ησ.  (8)

In a second additional simulation run, a second corner delay value (τ₂) is determined by setting nFET channel length value at its nominal channel length value (L_(nfet,nom)) but offsetting the pFET channel length value by a standard deviation (σ), i.e., ΔL_(nfet,2)=0 and ΔL_(pfet,2)=ησ. In the linear approximation, the second corner delay value (τ₂) is also given by Eq. (6), τ₂=τ_(nom) +s ₁ ΔL _(nfet,2) +s ₂ ΔL _(pfet,2)=τ_(nom) +s ₂ησ.  (9)

In this case, the variance of the delay (σ_(τ) ²) and the standard deviation of the delay (σ_(τ)) are determined by Eqs. (1a) and (1b), respectively. In the linear approximation that follows, the value of the variance of the delay is obtained after using Eqs. (8) and (9), σ_(τ,corner) ²=σ²(s ₁ ² +s ₂ ²),  (10) which does not agree with Monte Carlo simulation result (7) in the linear region in that it lacks the partial correlation term, 2s₁s₂C_(nfet,pfet), and, thus, is not correct. Referring to the graph of FIG. 1B, the inaccuracy of the prior art corner/sensitivity methods is illustrated by the fact that there is no correlation between the offset of NFET channel length value (L_(nfet)) and the offset of PFET channel length value (L_(pfet)), since (ΔL_(nfet,1))(ΔL_(pfet,1))=0 and (ΔL_(nfet,2))(ΔL_(pfet,2))=0.

In view of the foregoing, disclosed herein are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations between corresponding statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value (e.g., a nominal delay value) with all statistical model parameters of the field effect transistors set at their nominal model parameter values (e.g., nominal channel length values, nominal threshold voltage values, nominal overlap capacitance values, nominal channel width values, etc.). Then, multiple additional simulation runs are performed to determine corner performance values (e.g., corner delay values). In each successive additional simulation run, the statistical model parameters of the different types of field effect transistors are properly set at different model parameters values (e.g., different channel length values, different threshold voltage values, different overlap capacitance values, different channel width values, etc.) that are offset from their nominal model parameter values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined. This technique preserves the partial correlations between the statistical model parameters of the different types of field effect transistors and does so without requiring the performance of a large number of simulations and without requiring knowledge of the sensitivities of the performance target.

More particularly, referring to FIG. 2, disclosed herein is a computer system 200 for modeling integrated circuit performance. This computer system 200 can be implemented, for example, in a computer hardware environment such as that described in detail below and depicted in FIG. 3. Alternatively, this computer system 200 can be implemented on any other computerized device or network of devices having the required data storage and processing capability to perform the described processes (e.g., a distributed computer system of multiple autonomous computers that communicate through a computer network, a laptop computer, a tablet computer, etc.).

In any case, this computer system 200 can comprise one or more memory devices 210 (e.g., data storage devices) and one or more processors 220 in communication with the memory device(s) 210 (e.g., over a system bus 201 or over any wired or wireless communication network).

The memory device(s) 210 can store information including, but not limited to, a design 211 of an integrated circuit. This integrated circuit can comprise at least two different types of field effect transistors. For example, the integrated circuit can comprise any two or more of the following: a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), a regular threshold voltage p-type field effect transistor (RVT pFET), a high threshold voltage n-type field effect transistor (HVT nFET), a high threshold voltage p-type field effect transistor (HVT pFET), etc.

The memory device(s) 210 can further store a variety of software tools 230 comprising programs of instructions executable by the processor(s) 220 for performing various different functions. These software tools 230 can include, but are not limited to, a performance analysis tool 231 (e.g., a statistical static timing analysis (SSTA) tool) and a calculation tool 232.

The processor(s) 220 can access the memory device(s) 210 and, particularly, the information stored therein including, the design 211 and the software tools 230, and using this information can generate a corner model for a performance target that preserves partial correlations between corresponding statistical model parameters of each of the different types of field effect transistors. The performance target can comprise, for example, delay of logic gates. The corresponding statistical model parameters can comprise, for example, channel lengths, threshold voltage, overlap capacitances or channel widths. It should be understood that a single processor can execute the software tools 230 in order to generate the corner model, as described. Alternatively, any number of two or more different processors can execute the software tools 230 in order to generate the corner model, as described.

In order to generate such a corner model, the processor(s) 220 can execute the performance analysis tool 231. This performance analysis tool 231 can perform (i.e., can be adapted to perform, can be programmed to perform, etc.) an initial simulation run to determine a nominal performance value. During the initial simulation run, the values of the corresponding statistical model parameters (e.g., the corresponding channel length values, the corresponding threshold voltage values, the corresponding overlap capacitance values or corresponding channel width values) of the two or more different types of field effect transistors can be set at their respective nominal model parameter values (e.g., nominal channel length values, nominal threshold voltage values, nominal overlap capacitance values, or nominal channel width values, respectively).

The performance analysis tool 231 can further perform multiple additional simulation runs to determine corner performance values. During each successive additional simulation run, the values of the corresponding statistical model parameters (e.g., the corresponding channel length values, the corresponding threshold voltage values, the corresponding overlap capacitance values or the corresponding channel width values) of the two or more different types of field effect transistors can be set at different model parameter values that are offset from their respective nominal model parameters values. The different model parameter values used for each successive additional simulation run are chosen in such a way that all given partial correlations among the corresponding statistical model parameters are preserved after all of the additional simulation runs are performed. For example, they can be chosen, as discussed in greater detail below, based on a set of statistical models generated for the statistical model parameters and different types of field effect transistors at issue. Techniques for generating statistical models (e.g., statistical models for channel lengths or other parameters) are well known in the art and those skilled in the art will recognize that such statistical models are typically generated prior to running Monte Carlo simulations. Thus, the details of statistical model generation are omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments.

Once the initial and additional simulation runs are preformed, the processor(s) 220 can execute the calculation tool 232. This calculation tool 232 can determine (i.e., can be adapted to determine, can be programmed to determine, etc.) statistical information related to the performance target (τ) (e.g., related to delay of the logic gates). This statistical information can include, but is not limited to, a variance (σ²) and/or a standard deviation (σ) for the performance target, based on performance differences between each of the corner performance values and the nominal performance value. For example, the calculation tool 232 can determine the standard deviation (σ) for the performance target by solving a root sum of squares (RSS) expression for each of the corner performance values and the nominal performance value. This technique can be used to acquire the same variance (σ²) and/or standard deviation (σ) for the performance target as would be acquired using the Monte-Carlo technique described above. However, this technique has the added advantages of not requiring the performance of hundreds, thousands or tens of thousands of simulations and not requiring knowledge of the sensitivities of the performance target.

For illustration purposes, the operation of the computer system 200 of FIG. 2 is described in more detail below with respect to an integrated circuit that comprises a simple complementary metal oxide semiconductor (CMOS) inverter 400, as shown in FIG. 4, with a first field effect transistor (e.g., an n-type field effect transistor (nFET) 401) electrically connected in series to a second field effect transistor (e.g., a p-type field effect transistor (pFET) 402). The performance target at issue can comprise delay (τ) of logic gates and the corresponding statistical model parameters at issue with partial correlations can comprise channel length values (L_(nfet) and L_(pfet)) for the nFET 401 and pFET 402, respectively. It should be understood that this description of the operation of the computer system 200 is not intended to be limiting. As mentioned above, the integrated circuit could comprise any number of two or more field effect transistors having corresponding statistical model parameters with partial correlations. Furthermore, the corresponding statistical model parameters at issue could comprise any other model parameters (e.g., threshold voltages (Vt), overlap capacitances, channel widths, etc.).

In this case, the performance analysis tool 231 can comprise, for example, a statistical static timing analysis (SSTA) tool. The SSTA tool 231 can perform (i.e., can be adapted to perform, can be programmed to perform, etc.) an initial simulation run to determine a nominal delay value (τ_(nom)). During the initial simulation run, the corresponding statistical model parameter values and, particularly, the corresponding channel length values of the nFET 401 and pFET 402 can be set at their respective nominal channel length values (L_(nfet,nom) and L_(pfet,nom)), as indicated by the design 211.

The SSTA tool 231 can further perform multiple additional simulation runs to determine corner delay values (τ₁ and τ₂). During each successive additional simulation run, the corresponding channel length values of the nFET 401 and pFET 402 can be set at different channel length values (L_(nfet) and L_(pfet), respectively) that are both offset from their respective nominal channel length values (L_(nfet,nom) and L_(pfet,nom)) in correlated ways. The channel length values (L_(nfet) and L_(pfet), respectively) used for each successive additional simulation run are chosen in such a way that all given partial correlations among the channel lengths are preserved after all of the additional simulation runs are performed. For example, they can be chosen, as discussed in greater detail below, based on a set of statistical models generated for the channel length values (L_(nfet) and L_(pfet)) of the nFET and pFET, respectively. As mentioned above, techniques for generating statistical models (e.g., statistical models for channel lengths or other parameters) are well known in the art and those skilled in the art will recognize that such statistical models are typically generated prior to running Monte Carlo simulations. Thus, the details of statistical model generation are omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments.

Thus, in an IC comprising two different types of field effect transistors, each successive additional simulation run can comprise setting a first predetermined statistical model parameter value for the first field effect transistor equal to a first nominal model parameter value for that first field effect transistor plus a first specific multiple of a standard deviation and setting a second predetermined statistical model parameter value for the second field effect transistor equal to a second nominal model parameter value for that second field effect transistor plus a second specific multiple of the standard deviation, where the first and second specific multiples comprise multiples associated with random variables representative of partial correlations within a set of statistical models provided for the IC. More specifically, in the example of the simple CMOS inverter 400 discussed above, each successive additional simulation run can comprise setting a first predetermined channel length value (L_(nfet)) for the first field effect transistor (i.e., for the nFET 401) and a second predetermined channel length value (L_(pfet)) for the second field effect transistor (i.e., for the pFET 402). In a first additional simulation run, this first predetermined channel length value (L_(nfet)) can be set such that it is equal to a first nominal channel length value for the nFET 401 (L_(nfet,nom)) plus an nFET's offset multiplier times a standard deviation (i.e., ηα₁₁σ=ηa₁σ) for the first random number g₁ in the given statistical model of the FET channel lengths. In the first additional simulation run, the second predetermined channel length value (L_(pfet)) can be set such that it is equal to a second nominal channel length value for the pFET 402 (L_(pfet,nom)) plus a pFET's offset multiplier times a standard deviation (i.e., ηα₂₁σ=ηa₁σ) of the first random number g₁ in the given statistical model of the FET channel lengths. The results of the first additional simulation run can be used to obtain a first corner delay value τ₁. In a second additional simulation run, the first predetermined channel length value (L_(nfet)) can be set such that it is equal to a first nominal channel length value for the nFET 401 (L_(nfet,nom)) plus an nFET's offset multiplier times a standard deviation (i.e., ηα₁₂σ=ηa₂σ) of the second random number g₂ in the given statistical model of the FET channel lengths. In this second additional simulation run, the second predetermined channel length value (L_(pfet)) can be set such that it is equal to a second nominal channel length value for the pFET 402 (L_(pfet) plus a pFET's offset multiplier times a standard deviation (i.e., ηα₂₂σ=−ηa₂σ) of the second random number g₂ in the given statistical model of the FET channel lengths. The results of this second additional simulation run can be used to obtain a second corner delay value τ₂.

It should be noted that the value of each of the offset multipliers ηα_(i,j) (also referred to herein as offset coefficients) can be acquired from a set of statistical models, such as those shown in Eqs. (2a)-(2b), which is provided at the start of the disclosed corner model generation process and which illustrates the partial correlation between the corresponding statistical model parameters (e.g., between the channel length values (L_(nfet) and L_(pfet))). For example, for a simple CMOS inverter, the offset multipliers α_(i,j) can be acquired from a set of statistical model for channel length values (L_(nfet) and L_(pfet)) and can be, for example: ηα₁₁=ηa₁ (e.g., 0.8η) and ηα₁₂=ηa₂ (e.g., 0.6η), respectively for the nFET and ηα₂₁=ηa₁ (e.g., 0.8η) and ηα₂₂=−ηa₂ (e.g., −0.6η), respectively for the pFET). It should be understood that the exemplary offset multipliers provided above are for illustration purposes only and that, depending upon the particular statistical models provided, these offset multiplier will vary but, in any case, will be between −3 and 3.

In this case, in a first additional simulation run, each of the first (nFET) channel length value (L_(nfet)) of the nFET 401 and the second (pFET) channel length value (L_(pfet)) of the pFET 402 can be offset along g₁ direction. Specifically, L_(nfet) and L_(pfet) can be offset from their respective nominal channel length values (L_(nfet,nom) and L_(pfet,nom)) by the multiplier for the first random variable g₁ in the set of statistical models for channel lengths (2a)-(2b): L _(nfet,1) =L _(nfet,nom) +a ₁ησ,  (11a) L _(pfet,1) =L _(pfet,nom) +a ₁ησ,  (11b) where the parameter η can be +1, +2, +3, −1, −2, or −3, etc. Based on the results of the first additional simulation run, a first corner delay value (τ₁) can be obtained. Specifically, in the linear approximation, the first corner delay value (τ₁) can be determined using the following expression, where Eqs. (11a) and (11b) are substituted into Eq. (6): τ₁+τ_(nom) +s ₁ a ₁ ησ+s ₂ a ₁ησ=τ_(nom) +a ₁ησ(s ₁ +s ₂).  (12)

Similarly, in a second additional simulation run, each of the first (nFET) channel length value (L_(nfet)) of the nFET 401 and the second (pFET) channel length value (L_(pfet)) of the pFET 402 can be offset along g₂ direction. Specifically, L_(nfet) and L_(pfet) can be offset from their respective nominal values (L_(nfet,nom) and L_(pfet,nom)) by the multiplier for the second random variable g₂ in the set of statistical models for channel lengths (2a)-(2b): L _(nfet,2) =L _(nfet,nom) +a ₂ησ,  (13a) L _(pfet,2) =L _(pfet,nom) −a ₂ησ.  (13b)

Based on the results of the second additional simulation run, a second corner delay value (τ₂) can be obtained. Specifically, in the linear approximation, the second corner delay value (τ₂) can be determined using the following expression, wherein Eqs. (13a) and (13b) are substituted into Eq. (6): τ₂=τ_(nom) +s ₁ a ₂ ησ−s ₂ a ₂ησ=τ_(nom) +a ₂ησ(s ₁ s ₂).  (14)

Once the initial and additional simulation runs are preformed as described above, the processor(s) 220 can execute the calculation tool 232. This calculation tool 232 can determine (i.e., can be adapted to determine, can be programmed to determine, etc.) a variance for the delay at the corners (σ_(τ,corner) ²) and, thereby the standard deviation for the delay value (σ_(τ,corner)) based on performance differences between each of the corner performance values and the nominal performance value. For example, the calculation tool 232 can determine the variance (σ_(τ,corner) ²) and, thereby the standard deviation (σ_(τ)) by calculating a root sum of squares (RSS) expression for each of the corner delay values (τ₁ and τ₂) and the nominal delay value (τ_(nom). Specifically, the variance (σ_(τ,corner) ²) can be obtained from Eq. (1a).

This approach to generating a corner model has merit for the following reasons. The variances of L_(nfet) and L_(pfet) are preserved after (2+1) runs. Similar to Eq. (1a), the variance of L_(nfet) in the corner approach and the variance of L_(pfet) in the corner approach are preserved, as follows:

$\begin{matrix} {{\sigma_{{nfet},{corner}}^{2} = {{\frac{1}{\eta^{2}}\left\lbrack {\left( {L_{{nfet},1} - L_{{nfet},{nom}}} \right)^{2} + \left( {L_{{nfet},1} - L_{{nfet},{nom}}} \right)^{2}} \right\rbrack} = {{\sigma^{2}\left( {a_{1}^{2} + a_{2}^{2}} \right)} = \sigma^{2}}}},{and}} & \left( {15a} \right) \\ {\sigma_{{pfet},{corner}}^{2} = {{\frac{1}{\eta^{2}}\left\lbrack {\left( {L_{{pfet},1} - L_{{pfet},{nom}}} \right)^{2} + \left( {L_{{pfet},2} - L_{{pfet},{nom}}} \right)^{2}} \right\rbrack} = {{\sigma^{2}\left( {a_{1}^{2} + a_{2}^{2}} \right)} = {\sigma^{2}.}}}} & \left( {15b} \right) \end{matrix}$

Additionally, the correlation coefficient is also preserved after (2+1) runs. Similar to Eq. (1a), the correlation coefficient between L_(nfet) and L_(pfet) in the corner approach is

$\begin{matrix} {C_{{nfet},{pfet}}^{corner} = {{\frac{1}{\eta^{2}\sigma^{2}}{\sum\limits_{m = 1}^{2}\;{\left( {L_{{nfet},m} - L_{{nfet},{nom}}} \right)\left( {L_{{pfet},m} - L_{{pfet},{nom}}} \right)}}} = {{a_{1}^{2} - a_{2}^{2}} = {C_{{nfet},{pfet}}.}}}} & (16) \end{matrix}$

Furthermore, in the linear approximation, the relation between the variance (σ_(τ,corner) ²) of the delay at the corners and the sensitivities are obtained by substituting Eqs. (11a), (11b), (13a), and (13b) into Eq. (1a) and using Eq. (4), σ_(τ,corner) ² =a ₁ ²σ²(s ₁ +s ₂)² +a ₂ ²σ²(s ₁ −s ₂)²=σ² [s ₁ ² +s ₂ ²+2(a ₁ ² −a ₂ ²)s ₁ s ₂]=σ²(s ₁ ² +s ₂ ²+2s ₁ s ₂ C _(nfet,pfet)),  (17) which equals the variance expression of Eq. (7) from the Monte Carlo approach. Since the variance expression of Eq. (17) includes the third sensitivity term of 2s₁s₂C_(nfet,pfet) as seen in the Monte-Carlo variance expression of Eq. (7) shown above, this technique does accurately preserve the partial correlation between the model parameters of the nFET and pFET (as illustrated by the fact that in the graph of FIG. 5 delay values (τ₁) and (τ₂) land on the curve 501, which represents the partial correlation), and thereby accurately calculates the standard deviation for delay (σ_(τ)).

It should be noted that in the example of the simple CMOS inverter provided above the total number M of additional simulation runs is equal to the total number N of corresponding statistical model parameters, which is equal to the total number K of different types of FETs. Specifically, in this simple CMOS inverter example, where only a single statistical model parameter (e.g., a channel length, a threshold voltage, an overlap capacitance, or a channel width) of each of the two different types of FETs in an IC is considered, the total number N of corresponding statistical model parameters is equal to the total number K of different types of FETs (i.e., one statistical model parameter and, particularly, the channel length of each of the two different types of FETs). However, when multiple and, particularly, some number J of different types of statistical model parameters (e.g., any two or more of channel length, threshold voltage, overlap capacitance, channel width, etc.) of each of the different types of FETs in an IC are to be considered, the total number N of corresponding statistical model parameters and, thereby the total number M of additional simulation runs required can be greater than the total number K of different types of FETs and, particularly, can be equal to the product of J (i.e., the total number of different types of statistical model parameters of each different type of FET to be considered) and K (i.e., the total number of different types of FETs). Thus, for example, to determine the delay of a simple CMOS inverter considering two different types of statistical model parameters (e.g., both channel length and threshold voltage), the total number N of corresponding statistical model parameters at issue and, thereby the total number M of multiple additional simulation runs will be equal to JK=2×2=4.

It should be understood that operation of the computer system 200 can be essentially the same for an exemplary integrated circuit that comprises more than two different types of field effect transistors (e.g., four different types of field effect transistors including a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), and a regular threshold voltage p-type field effect transistor (RVT pFET)). In this case, if only one statistical model parameter (e.g., channel length) is to be considered (i.e., if J=1) and the number of different types of FETs is four (i.e., K=4), then the total number N of corresponding statistical model parameters will be equal to four (i.e., N=JK=1×4=4) and the total number M of additional simulation runs required will also be equal to four. In this case, if two statistical model parameters (e.g., channel length and threshold voltage) are to be considered (i.e., if J=2) and the number of different types of FETs is four (i.e., K=4), then the total number N of corresponding statistical model parameters will be equal to eight (i.e., N=JK=2×4=4) and the total number M of additional simulation runs required will also be equal to four.

For example, FIG. 6 is a correlation matrix illustrating exemplary partial correlations that may exist between the channel lengths of four different types of field effect transistors in an integrated circuit. Additionally, Eqs. (18a)-(18d) below illustrate an exemplary set of four statistical models for the channel lengths of the four different types of field effect transistors: L _(lvtn) =L _(lvtn,nom)+σ(√{square root over (46)}g ₁+√{square root over (14)}g ₂+2g ₃)/8,  (18a) L _(rvtn) =L _(rvtn,nom)+σ(√{square root over (46)}g ₁+√{square root over (14)}g ₂+2g ₃)/8,  (18b) L _(lvtp) =L _(lvtp,nom)+σ(√{square root over (46)}g ₁+√{square root over (14)}g ₂+2g ₄)/8,  (18c) L _(rvtp) =L _(rvtp,nom)+σ(√{square root over (46)}g ₁+√{square root over (14)}g ₂+2g ₄)/8,  (18d) where each of g_(m) (m=1, 2, 3, 4) is an independent random variable of mean zero and standard deviation one (M=4 in this example),

g _(m)

=0, m=1,2, . . . ,M;

g _(m) ²

=1, m=1,2, . . . ,M;

g _(m) g _(n)

=0, m,n=1,2, . . . ,M, m≠n.  (19)

In this case, the initial simulation run can be performed with the channel lengths of each of the four different types of field effect transistors (i.e., L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) set to their nominal channel lengths (i.e., L_(lvtn,nom), L_(rvtn,nom), L_(lvtp,nom), and L_(rvtp,nom)) to determine a nominal delay value (τ_(nom)). Then, four additional simulation runs can be performed with the channel lengths of each of the four different types of field effect transistors set, as follows, at different channel length values that are offset from their respective nominal channel length values in correlated ways.

For the first additional simulation run, the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) of each of the four different transistors can be set such that they are offset along the g₁ direction. Specifically, each of the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) can be offset, as follows, from their respective nominal channel length values (L_(lvtn,nom), L_(rvtn,nom), L_(lvtp,nom), and L_(rvtp,nom)) by the multiplier for the first random variable g₁ in the set of statistical models for channel lengths (18a)-(18d): L _(lvtn,1) =L _(lvtn,nom)+√{square root over (46)}ησ/8,  (20a) L _(rvtn,1) =L _(rvtn,nom)+√{square root over (46)}ησ/8,  (20b) L _(lvtp,1) =L _(lvtp,nom)+√{square root over (46)}ησ/8,  (20c) L _(rvtp,1) =L _(rvtp,nom)+√{square root over (46)}ησ/8,  (20d) where the parameter η can be +1, +2, +3, −1, −2, or −3, etc. Based on the results of the first additional simulation run, a first corner performance value (τ_(i)) can be obtained.

For the second additional simulation run, the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) of each of the four different transistors can be set such that they are offset along the g₂ direction. Specifically, each of the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) can be set, as follows, such that they are offset from their respective nominal channel length values (L_(lvtn,nom), L_(rvtn,nom), L_(lvtp,nom), and L_(rvtp,nom)) by the multiplier for the second random variable g₂ in the set of statistical models for channel lengths (18a)-(18d): L _(lvtn,2) =L _(lvtn,nom)+√{square root over (14)}ησ/8,  (21a) L _(rvtn,2) =L _(rvtn,nom)+√{square root over (14)}ησ/8,  (21b) L _(lvtp,2) =L _(lvtp,nom)−√{square root over (14)}ησ/8,  (21c) L _(rvtp,2) =L _(rvtp,nom)−√{square root over (14)}ησ/8.  (21d)

Based on the results of the second additional simulation run, a second corner performance value (τ₂) can be obtained.

For the third additional simulation run, the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) of each of the four different transistors can be set such that they are offset along g₃ direction. Specifically, each of the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) can be set, as follows, such that they are offset from their respective nominal channel length values (L_(lvtn,nom), L_(rvtn,nom), L_(lvtp,nom), and L_(rvtp,nom)) by the multiplier for the third random variable g₃ in the set of statistical models for channel lengths (18a)-(18d): L _(lvtn,3) =L _(lvtn,nom)+ησ/4,  (22a) L _(rvtn,3) =L _(rvtn,nom)−ησ/4,  (22b) L _(lvtp,3) =L _(lvtp,nom),  (22c) L _(rvtp,3) =L _(rvtp,nom).  (22d)

It should be noted that as illustrated by Eqs. (22c) and (22d), in any given additional simulation run, one or more statistical model parameters may not be offset. However, in all such additional simulation runs, at least one of statistical model parameters must have an offset. Based on the results of the third additional simulation run, a third corner performance value (τ₃) can be obtained.

Finally, for the fourth additional simulation run, the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) of each of the four different transistors can be set such that they are offset along the g₄ direction. Specifically, each of the channel lengths (L_(lvtn), L_(rvtn), L_(lvtp), and L_(rvtp)) can be set, as follows, such that they are offset from their respective nominal channel length values (L_(lvtn,nom), L_(rvtn,nom), L_(lvtp,nom), and L_(rvtp,nom)) by the multiplier for the fourth random variable g₄ in the set of statistical models for channel lengths (18a)-(18d): L _(lvtn,4) =L _(lvtn,nom),  (23a) L _(rvtn,4) =L _(rvtn,nom),  (23b) L _(lvtp,4) =L _(lvtp,nom)+ησ/4,  (23c) L _(rvtp,4) =L _(rvtp,nom)−ησ/4,  (23d)

Based on the results of the fourth additional simulation run, a fourth corner performance value (τ₄) can be obtained.

After obtaining the nominal performance value (τ_(nom)) and the four corner performance values (τ₁, τ₂, τ₃, and τ₄), the variance (σ_(τ,corner) ²) and, thereby the standard deviation (σ_(τ,corner)) of the corner performance target (τ) can be determined using the following expression, which is a generalization of Eq. (1a):

$\begin{matrix} {\sigma_{\tau,{corner}}^{2} = {\frac{1}{\eta^{2}}{\sum\limits_{m = 1}^{4}\;{\left( {\tau_{m} - \tau_{nom}} \right)^{2}.}}}} & (24) \end{matrix}$

Consider also a set of coupled relations for N statistical model parameters p₁, p₂, . . . , p_(N), which is already provided,

$\begin{matrix} {{p_{i} = {p_{i,{nom}} + {\sigma_{i}{\sum\limits_{m = 1}^{M}\;{\alpha_{i,m}g_{m}}}}}},{i = 1},2,\cdots\mspace{14mu},N,} & (25) \end{matrix}$ where each of g_(m) is an independent random variable of mean zero and standard deviation one (see Eq. (19)). Coefficients α_(i,m) satisfy normalization conditions,

$\begin{matrix} {{{\sum\limits_{m = 1}^{M}\;\alpha_{i,m}^{2}} = {C_{i,i} = 1}},{i = 1},2,\cdots\mspace{14mu},N,} & (26) \end{matrix}$ such that

(Δp _(i))²

=

(p _(i) −p _(i,nom))²

=σ_(i) ² , i=1,2, . . . ,N  (27)

Coefficients α_(i,m) further satisfy the following relations, and correlation relations

$\begin{matrix} {{{\sum\limits_{m = 1}^{M}\;{\alpha_{i,m}\alpha_{j,m}}} = C_{i,j}},i,{j = 1},2,\cdots\mspace{14mu},N,} & (28) \end{matrix}$ such that

(Δp _(i))(Δp _(j))

=

(p _(i) −p _(i,nom))(p _(j) −p _(j,nom))

=σ_(i)σ_(j) C _(i,j) , i,j=1,2, . . . ,N,  (29) where C_(i,j) are correlation coefficients. In this case, the number of independent random variables and, thereby the number M of additional simulation runs required can be equal to, larger than, or smaller than the total number of corresponding statistical model parameters N. Specifically, the statistical model parameters p₁, p₂, . . . , p_(N) can be a mix of nFET channel length, pFET channel length, nFET overlap capacitance, pFET overlap capacitance, nFET threshold voltage, pFET threshold voltage, nFET channel width, pFET channel width, etc.

For example, for an RVT inverter comprising an RVT nFET and an RVT pFET where two different types of statistical model parameters, namely, channel length and threshold voltage, are considered, the total number N of corresponding statistical model parameter equals KJ=2×2=4. Given the above statistical model of Eq. (25) above, a corner model can be acquired by first performing an initial simulation run during which each statistical model parameter is set at its respective nominal value, p _(i,0) =p _(i,nom) , i=1,2, . . . ,N,  (30) in order to obtain a nominal performance value τ_(nom). Then, M additional simulation runs can be performed. During the mth (m=1, 2, . . . , M) additional simulation run, the statistical model parameters can be offset along the g_(m) direction. Specifically, the statistical model parameters can be set as follows: p _(i,m) =p _(i,nom)+σ_(i)(ηα_(i,m)), i=1,2, . . . ,N, m=1,2, . . . ,M,  (31) a mth additional simulation run can be performed and, based on the results of the mth additional simulation run, a mth corner performance value τ_(m) can be obtained as discussed above. Again, the parameter η in Eq. (31) can be +1, +2, +3, −1, −2, or −3, etc. The range of the product ηα_(i,m) is from −|η| to |η|. Alternatively, we say that the range of the product ηα_(i,m) is from −3 to +3.

Finally, after obtaining the nominal performance value τ_(nom) and the corner performance values at each additional simulation run (i.e., τ₁, τ₂, . . . , τ_(M)), the following expressions, which are a generalization of Eq. (24),can be used to obtain the variation (σ_(τ,corner) ²) of the performance target τ:

$\begin{matrix} {{\sigma_{\tau,{corner}}^{2} = {\frac{1}{\eta^{2}}{\sum\limits_{m = 1}^{M}\;{\left( {\tau_{m} - \tau_{nom}} \right)^{2}.}}}},{and}} & \left( {32a} \right) \\ {\sigma_{\tau,{corner}} = {{\frac{1}{\eta}\left\lbrack {\sum\limits_{m = 1}^{M}\;\left( {\tau_{m} - \tau_{nom}} \right)^{2}} \right\rbrack}^{\frac{1}{2}}.}} & \left( {32b} \right) \end{matrix}$

Namely, the standard deviation of the corner delay (σ_(τ, corner)) is a root sum of squares (RSS) of the differences between corner delays and nominal delay. This approach to generating a corner model has merit for the following reasons. The variances of p₁, p₂, . . . , p_(N) are preserved after (M+1) runs. Similar to Eq. (32), the variance of p_(i) in the corner approach can be solved for as follows:

$\begin{matrix} {{\sigma_{i,{corner}}^{2} = {{\frac{1}{\eta^{2}}{\sum\limits_{m = 1}^{M}\;\left( {p_{i,m} - p_{i,{nom}}} \right)^{2}}} = {{\sigma_{i}^{2}{\sum\limits_{m = 1}^{M}\;\alpha_{i,m}^{2}}} = \sigma_{i}^{2}}}},{i = 1},2,\cdots\mspace{14mu},N,} & (33) \end{matrix}$ where Eqs. (31) and (26) have been used. Additionally, N(N−1)/2 correlation coefficients are also preserved after (M+1) runs. Similar to Eqs. (32a) and (33), the correlation coefficient between p_(i) and p_(j) in the corner approach can be solved for as follows:

$\begin{matrix} {{C_{i,j}^{corner} = {{\frac{1}{\eta^{2}\sigma_{i}\sigma_{j}}{\sum\limits_{m = 1}^{M}\;{\left( {p_{i,m} - p_{i,{nom}}} \right)\left( {p_{j,m} - p_{j,{nom}}} \right)}}} = {{\sum\limits_{m = 1}^{M}\;{\alpha_{i,m}\alpha_{j,m}}} = C_{i,j}}}},i,{j = 1},2,\cdots\mspace{14mu},N,} & (34) \end{matrix}$ where Eqs. (31) and (28) have been used. Furthermore, in the linear approximation, the standard deviation obtained from the corner approach is equals to that obtained from the Monte Carlo approach. In the linear approximation, a performance target is a linear function of variations of statistical parameters, as shown below:

$\begin{matrix} {{\tau \approx {\tau_{nom} + {\sum\limits_{i = 1}^{N}\;{s_{i}\;\left( {p_{i} - p_{i,{nom}}} \right)}}}},} & (35) \end{matrix}$ where s_(i) (i=1, 2, . . . , N) is a sensitivity of the performance target with respect to variation in the ith statistical model parameter and its value is not known. In terms of sensitivities s_(i), the variance and, thereby the standard deviation of the performance target from Monte Carlo simulations can be obtained analytically as follows:

$\begin{matrix} \begin{matrix} {\sigma_{\tau,{MC}}^{2} = {\left\langle \left( {\tau - \tau_{nom}} \right)^{2} \right\rangle = \left\langle \left( {{\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}\;{\sum\limits_{m = 1}^{M}\;\alpha_{i,m}}}},g_{m}} \right)^{2} \right\rangle}} \\ {= \left\langle {\left( {{\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}\;{\sum\limits_{m = 1}^{M}\;\alpha_{i,m}}}},g_{m}} \right)\left( {\sum\limits_{j = 1}^{N}\;{s_{j}\;\sigma_{j}\;{\sum\limits_{n = 1}^{M}\;{\alpha_{j,n}g_{n}}}}} \right)} \right\rangle} \\ {= \left\langle {\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}\;{\sum\limits_{j = 1}^{N}\;{s_{j}\;\sigma_{j}{\sum\limits_{m,{n = 1}}^{M}\;{\alpha_{i,m}\alpha_{j,n}g_{m}g_{n}}}}}}} \right\rangle} \\ {= {\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}{\sum\limits_{j = 1}^{N}\;{s_{j}\;\sigma_{j}{\sum\limits_{m,{n = 1}}^{M}\;{\alpha_{i,m}\alpha_{j,n}\left\langle {g_{m}g_{n}} \right\rangle}}}}}}} \\ {= {\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}{\sum\limits_{j = 1}^{N}\;{s_{j}\;\sigma_{j}{\sum\limits_{m = 1}^{M}\;{\alpha_{i,m}\alpha_{j,m}}}}}}}} \\ {= {\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}{\sum\limits_{j = 1}^{N}\;{s_{j}\;\sigma_{j}{C_{i,j}.}}}}}} \end{matrix} & (36) \end{matrix}$

In terms of sensitivities s_(i), the variance (σ_(τ,corner) ²) and, thereby the standard deviation (σ_(τ, corner)) of the performance target (τ) from our corner approach can also be found analytically by substituting Eqs. (35) and (31) into Eq. (32a) and using Eq. (28), as follows:

$\begin{matrix} \begin{matrix} {\sigma_{\tau,{corner}}^{2} = {\frac{1}{\eta^{2}}{\sum\limits_{m = 1}^{M}\;{\sum\limits_{i = 1}^{N}\;{{s_{i}\left( {p_{i} - p_{i,{nom}}} \right)}{\sum\limits_{j = 1}^{N}\;{s_{j}\left( {p_{j} - p_{j,{nom}}} \right)}}}}}}} \\ {= {\sum\limits_{m = 1}^{M}\;{\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}\;\alpha_{i,m}{\sum\limits_{j = 1}^{N}\;{s_{j}\;\sigma_{j}\;\alpha_{j,m}}}}}}} \\ {= {\sum\limits_{i = 1}^{N}\mspace{11mu}{s_{i}\;\sigma_{i}{\sum\limits_{j = 1}^{N}\mspace{11mu}{s_{j}\;\sigma_{j}{\sum\limits_{m = 1}^{M}\;{\alpha_{i,m}\alpha_{j,m}}}}}}}} \\ {{= {\sum\limits_{i = 1}^{N}\;{s_{i}\;\sigma_{i}{\sum\limits_{j = 1}^{N}\;{s_{j}\;\sigma_{j}C_{i,j}}}}}},} \end{matrix} & (37) \end{matrix}$ which is identical to Eq. (36).

Optionally, operation of the computer system 200 can be such that the total number M of additional simulation runs can be reduced to be equal to a lesser number I of the total number N of corresponding statistical model parameters and, particularly, to only that number I of the N corresponding statistical model parameters that actually affect a given performance target. Specifically, a determination can be made that, although an integrated circuit has a total number K of different types of FETs, only some number L of those K different types of FETs will actually affect the performance target at issue. Thus, the corner model can be generated based on a lesser number I of the N corresponding statistical model parameters, where I is equal to the product of the J (i.e., the total number of different types of statistical model parameters to be considered) and L (i.e., the lesser number of the K different types of FETs that actually affect the performance target). That is, I=JL, when L<K such that I<N. In this case, the total number M of additional simulation runs will be equal to I. However, in order to accomplish this, the full set of statistical models, which couples the N corresponding statistical model parameters together, must be reconstructed into a smaller, reconstructed set of statistical models, which couples together the statistical model parameters of only those L FETs that affect the performance target. Thus, in this reconstructed set, the partial correlations between the statistical model parameters of the L FETs are preserved; however, any correlations between the statistical model parameters of the L FETs and the statistical model parameters of the rest of the FETs (i.e., the FETs that do not affect the performance target) are uncoupled.

For example, an exemplary integrated circuit may comprise four different types of field effect transistors (i.e., K=4) including a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), and a regular threshold voltage p-type field effect transistor (RVT pFET). Eqs. (18a)-(18d) above illustrate the full set of four statistical models for the four different types of FETs in this integrated circuit, when only a single type of statistical model parameter, namely, channel length, is considered. Typically, in this case, the total number M of additional simulations required for corner model generation would be equal to the total number N of corresponding statistical model parameters, which would be equal to KJ=4×1=4. However, if a determination is made that in this integrated circuit a lesser number L (e.g., only RVT nFET and RVT pFET) of the total number K of the different types of field effect transistors are known to affect the performance target (e.g., delay of an inverter), then the additional simulation runs can be focused only on this pair of transistors, RVT nFET and RVT pFET and the number M of additional simulation runs will be equal to I, which is equal to the product of J and L. However, in order to accomplish this, the full set of four statistical models as shown in Eqs. (18a)-(18d), which couples the four corresponding statistical model parameters and, particularly, the four channel lengths of the four different types of FETs together, must be reconstructed into a smaller, reconstructed set of statistical models as shown in Eqs. (38a)-(38b) below, which couples together the statistical model parameters and, particularly, the channel lengths of only the RVT nFET and RVT pFET that affect the performance target.

Specifically, in this case, FIG. 7 is a correlation matrix illustrating exemplary partial correlations between the channel lengths of only this pair of transistors, RVT nFET and RVT pFET, and not the other transistors, LVT nFET and LVT pFET, within the integrated circuit. In this case, based on the reduced correlation matrix in FIG. 7, the full set of statistical models as shown in Eqs. (18a)-(18d), which couples together the four channel lengths of the four different types of FETs, can be reconstructed into a reconstructed set of statistical models, as shown in Eqs. (38a)-(38b) below, which couples together the channel lengths of only RVT nFET and RVT pFET. In this reconstructed set, the partial correlations between the statistical model parameters and, particularly, the channel lengths of RVT nFET and RVT pFET are preserved; however, any correlations between the statistical model parameters and, particularly, the channel lengths of the LVT nFET and LVT pFET are uncoupled. L _(rvtn) =L _(rvtn,nom)+σ(√{square root over (3)}g ₁ +g ₂)/2,  (38a) L _(rvtp) =L _(rvtp,nom)+σ(√{square root over (3)}g ₁ −g ₂)/2.  (38b)

After reconstructing the full set of statistical models into the smaller, reconstructed set of statistical models (38a) and (38b), the initial simulation run for the corner model can be performed, as discussed above, to determine a nominal delay value (τ_(nom)). Then, only two additional simulation runs need to be performed with the channel lengths of RVT nFET and RVT pFET set, using the reconstructed set of statistical models of Eqs. (38a) and (38b), at different channel length values that are offset from their respective nominal channel length values in correlated ways.

Specifically, for the first additional simulation run, the channel lengths (L_(rvtn) and L_(rvtp)) of only the transistors RVT nFET and RVT pFET can be set such that they are offset along the g₁ direction. Specifically, each of the channel lengths L_(rvtn) and L_(rvtp) can be offset from their respective nominal channel length values by the multiplier for the first random variable g₁ in the subset of statistical models for channel lengths (38a)-(38b): L _(rvtn,1) =L _(rvtn,nom)+√{square root over (3)}ησ/2,  (39a) L _(rvtp,1) =L _(rvtp,nom)+√{square root over (3)}ησ/2.  (39b)

Based on the results of the first additional simulation run, a first corner performance value τ₁ can be obtained.

For a second additional simulation run, the channel lengths (L_(rvtn) and L_(rvtp)) of only the transistors RVT nFET and RVT pFET can be set such that they are offset along the g₂ direction. Specifically, each of the channel lengths L_(rvtn) and L_(rvtp) can be offset from their respective nominal channel length values by the multiplier for the second random variable g₂ in the subset of statistical models for channel lengths (38a)-(38b): L _(rvtn,2) =L _(rvtn,nom)+ησ/2,  (40a) L _(pvtn,2) =L _(pvtn,nom)−ησ/2.  (40b)

Based on the results of the second additional simulation run, a second corner performance value τ₂ can be obtained. After obtaining nominal performance value (τ_(nom)) and two corner performance values (τ₁ and τ₂), Eqs. (1a)-(1b) can further be used to obtain the variance (σ_(τ,corner) ²) and the standard deviation (σ_(τ,corner)) of the performance target (τ).

Referring to the flow diagram of FIG. 8 in combination with FIG. 2, also disclosed herein is a computer-implemented method 800 for modeling integrated circuit performance.

This method can comprise storing, in one or more memory devices 210 (e.g., data storage devices), information including, but not limited to, a design 211 of an integrated circuit (802). This integrated circuit can comprise at least two different types of field effect transistors. For example, the integrated circuit can comprise any two or more of the following: a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), a regular threshold voltage p-type field effect transistor (RVT pFET), a high threshold voltage n-type field effect transistor (HVT nFET), a high threshold voltage p-type field effect transistor (HVT pFET), etc. The method can also comprise storing, in the memory device(s) 210, a variety of software tools 230 comprising programs of instructions executable by the processor(s) 220 for performing various different functions. These software tools 230 can include, but are not limited to, a performance analysis tool 231 (e.g., a statistical static timing analysis (SSTA) tool) and a calculation tool 232.

The method can further comprise accessing, by one or more processor(s) 220 from the memory device(s) 210, information stored therein including, the design 211 and the software tools 230 (804) and using this information can generate a corner model for a performance target that preserves partial correlations between corresponding statistical model parameter values of the different types of field effect transistors (806).

FIG. 9 is a flow diagram illustrating in greater detail the process 806 of generating a corner model for a performance target that preserves partial correlations between corresponding statistical model parameter values of the different types of field effect transistors. In order to generate such a corner model, setup for simulation runs can be performed. This set up can include, but is not limited to, acquiring specific information required to perform an initial simulation run and multiple additional simulation runs at processes 902-904, described in detail below (901).

This specific information can include, but is not limited to, the following: (1) a performance target (τ) at issue (e.g., delay); (2) the total number K and identity of the different types of field effect transistors used in the integrated circuit at issue, as indicated by the design; (3) optionally, the number L and identity of those of the K different types of field effect transistors that affect the performance target (τ) at issue such that K≧L; (4) the total number J and identity of the different types of statistical model parameters (e.g., channel length, threshold voltage, overlap capacitance, channel width, etc.) in each of the K different types of field effect transistors to be considered; (5) a full set of statistical models that preserves the partial correlations between all N corresponding statistical model parameters at issue, where N=JK; (6) optionally, a reconstructed set of statistical models associated with a lesser number I of the N corresponding statistical model parameters, where I=JL, when K>L, and where the reconstructed set includes statistical models for only those L FETs that affect the performance target, preserves the partial correlations between only the statistical model parameters of those L FETs and uncouples any correlations between the statistical model parameters of the L FETs and the statistical model parameters of the other FETs accounted for in the full set; and (7) the total number M of additional simulation runs to be performed, where M=N or, optionally, where M=I, when K>L and a reconstructed set of statistical models is available.

Then, an initial simulation run can be performed (e.g., by a processor 220 executing a performance analysis tool 231) to determine a nominal performance value (τ_(nom)) (902). During the initial simulation run, the corresponding statistical model parameter values of the two or more different types of field effect transistors can be set at their respective nominal model parameter values, as indicated in the design 211. This initial simulation run can be performed considering all of the N corresponding statistical model parameters for all of the K different types of field effect transistors.

Then, multiple additional simulation runs and, particularly, a predetermined number M of additional simulation runs can be performed (e.g., by a processor 220 executing a performance analysis tool 231) to determine corner performance values (904). During each successive additional simulation run at process 904, the corresponding statistical model parameter values of the two or more different types of field effect transistors can be set at different model parameter values that are offset from their respective nominal model parameters values in correlated ways. The different parameter values used for each successive additional simulation run are chosen in such a way that all given partial correlations among the corresponding statistical model parameters are preserved after all of the additional simulation runs are performed. Specifically, they can be chosen, as discussed in greater detail above with regard to the system 200, based on a set of provided statistical models.

It should be noted that the additional simulation runs can be performed using the full set of statistical models, which preserves the partial correlations between all of the N corresponding statistical model parameters of all of the K different types of field effect transistors, and, thus, so that the total number M of additional simulation runs is equal to the total number N of corresponding statistical model parameters, which, as discussed above, is equal to the product of the number K of different types of FETs and the number J of different types of statistical model parameters considered (i.e., M=N=KJ) (905 a).

Alternatively, if the total number K of the different types of FET in an integrated circuit under consideration is greater than the number L of those K different types of field effect transistors whose statistical model parameters actually affect the performance target (τ) at issue (i.e., if K>L), the additional simulation runs can be performed using the smaller reconstructed set of statistical models, which preserves only the partial correlations between the statistical model parameters of those L FETs that affect the performance target, and, thus, the total number M of additional simulation runs is equal to a lesser number I of the N corresponding statistical model parameters, where I=JL, by using only the smaller reconstructed set of statistical models referenced above and, thus, M=I=JL (905 b).

Once the initial and additional simulation runs are preformed as described statistical information related to the performance target (τ) can be determined (e.g., by a processor 220 executing a calculation tool 232) (906). This statistical information can include, but is not limited to, a variance (σ_(τ,corner) ²) and/or a standard deviation (σ_(τ, corner)) for the performance target (τ), based on performance differences between each of the corner performance values (τ₁, τ₂, . . . ) and the nominal performance value (τ_(nom)). For example, the standard deviation (σ_(τ, corner)) for the performance target can be determined by solving a root sum of squares (RSS) expression for each of the corner performance values and the nominal performance value. This technique can be used to acquire the same variance (σ_(τ,corner) ²) and/or standard deviation (σ_(τ, corner)) for the performance target as would be acquired using the Monte-Carlo technique described above. However, this technique has the added advantages of not requiring the performance of hundreds, thousands or tens of thousands of simulations and not requiring knowledge of the sensitivities of the performance target.

For illustration purposes, process steps 902-906 of FIG. 9 are described in more detail below with respect to an integrated circuit that comprises a simple complementary metal oxide semiconductor (CMOS) inverter 400, as shown in FIG. 4, with a first field effect transistor (e.g., an n-type field effect transistor (nFET) 401) electrically connected in series to a second field effect transistor (e.g., a p-type field effect transistor (pFET) 402). The performance target at issue can comprise delay (τ) and the corresponding statistical model parameters at issue with partial correlations can comprise channel length values (L_(nfet) and L_(pfet)) only for the nFET 401 and pFET 402, respectively. It should be understood that this description of the operation of the computer system 200 is not intended to be limiting. As mentioned above, the integrated circuit could comprise any number of two or more different types of field effect transistors having corresponding statistical model parameters with partial correlations. Furthermore, the corresponding statistical model parameter values could comprise any other model parameter values with partial correlations (e.g., threshold voltage values (Vt), overlap capacitance values, channel width values, etc.).

In this case, an initial simulation run can be performed at process 902 (e.g., by a processor 220 executing a performance analysis tool 231 and, particularly, a statistical static timing analysis (SSTA) tool) to determine a nominal delay value (τ_(nom)). During the initial simulation run, the corresponding statistical model parameter values of the nFET 401 and pFET 402 can be set at their respective nominal channel length values (L_(nfet,nom) and L_(pfet,nom)), as indicated by the design 211.

Then, multiple additional simulation runs can be performed at process 904 (e.g., by the processor 220 executing the SSTA tool) using a full set of statistical models that preserves the partial correlations between the channel lengths for the nFET 401 and pFET 402 to determine corner delay values (τ₁ and τ₂). During each successive additional simulation run at process 904, the corresponding channel length values of the nFET 401 and pFET 402 can be set at different channel length values (L_(nfet) and L_(pfet), respectively) that are both offset from their respective nominal channel length values (L_(nfet,nom) and L_(pfet,nom)) in correlated ways. The channel length values (L_(nfet) and L_(pfet), respectively) used for each successive additional simulation run are chosen in such a way that all given partial correlations among the channel lengths are preserved after all of the additional simulation runs are performed.

Specifically, in this case, in a first additional simulation run, each of the first (nFET) channel length value (L_(nfet)) of the nFET 401 and the second (pFET) channel length value (L_(pfet)) of the pFET 402 can be offset from their respective nominal channel length values (L_(nfet,nom) and L_(pfet,nom)) as shown in Eqs. (11a) and (11b) by the multiplier for the first random variable g₁ in the statistical models for channel lengths (2a)-(2b). Based on the results of the first additional simulation run, a first corner delay value (τ₁) can be obtained. Specifically, in the linear approximation, the first corner delay value (τ₁) can be determined using Eq. (12), where Eqs. (11a) and (11b) are substituted into Eq. (6). Similarly, in a second additional simulation run, each of the first (nFET) channel length value (L_(nfet)) of the nFET 401 and the second (pFET) channel length value (L_(pfet)) of the pFET 402 can be offset from their respective nominal values (L_(nfet,nom) and L_(pfet,nom)) as shown in Eqs. (11a) and (11b) by the multiplier for the second random variable g₂ in the statistical model for channel lengths (2a)-(2b). Based on the results of the second additional simulation run, a second corner delay value (τ₂) can be obtained. Specifically, in the linear approximation, the second corner delay value (τ₂) can be determined using Eq. (14), where Eqs. (13a) and (13b) are substituted into Eq. (6).

Once the initial and additional simulation runs are preformed at processes 902-904 as described above, a variance for the delay at the corners (σ_(τ,corner) ²) and, thereby the standard deviation for the delay value (σ_(τ, corner)) can be determined (e.g., by a processor 220 executing a calculation tool 232) based on performance differences between each of the corner performance values and the nominal performance value (906). For example, the variance (σ_(τ,corner) ²) and, thereby the standard deviation (σ_(τ, corner)) can be determined by solving a root sum of squares (RSS) expression for each of the corner delay values (τ₁ and τ₂) and the nominal delay value (τ_(nom)) using Eqs. (1a)-(1b).

It should be noted that in the example provided above where the integrated circuit comprises a simple CMOS inverter the additional simulation runs were performed using the full set of statistical models and the total number M of multiple additional simulation runs was equal to two and, particularly, equal to the total number N of corresponding statistical model parameters at issue, which, as discussed above, is equal to the product of the total number K of different field effect transistors (in this case, two) and the number J of different types of statistical model parameters considered for each different type of FET (in this case, one, namely channel length) (905 a).

Essentially the same method steps can be applied for an exemplary integrated circuit that comprises more than two different types of field effect transistors (e.g., four different types of field effect transistors including a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), and a regular threshold voltage p-type field effect transistor (RVT pFET)). In this case, the additional simulation runs can be performed using a full set of statistical models that preserves the partial correlations between the channel lengths of the four different types of FETs such that the total number M of multiple additional simulation runs will be equal to four and, particularly, will be equal the total number N of corresponding statistical model parameters at issue, which, as discussed above, is equal to the product of the total number K of different types of field effect transistors (in this case, four) and the number J of different types of statistical model parameters considered for each different type of FET (in this case, one, namely channel length) (905 a). See detailed discussion above regarding the correlation matrix of FIG. 6 and Eqs. (18a)-(18d) (see also Eqs. (22a)-(23d)).

Alternatively, however, the additional simulation runs can be performed using a smaller, reconstructed set of statistical models that preserves the partial correlation between the statistical model parameters of only those L of the K different types of field effect transistors that affect the performance target such that the total number M of additional simulation runs performed at process 904 can actually be less than the total number N of corresponding statistical model parameters (905 b). Specifically, prior to performing the initial simulation run at process 904 and the additional simulation runs at process 906, a determination can be made that, although an integrated circuit has a total number K of different types of FETs, only some lesser number L of those K different types of FETs will actually affect the performance target at issue. Thus, the corner model can be generated based on a lesser number I of the N corresponding statistical model parameters, where I is equal to the product of the J (i.e., the total number of different types of statistical model parameters to be considered) and L (i.e., the lesser number of the K different types of FETs that actually affect the performance target). That is, I=JL, when L<K such that I<N. In this case, the total number M of additional simulation runs will be equal to I. However, in order to accomplish this, the full set of statistical models, which couples the N corresponding statistical model parameters together, must be reconstructed into a smaller, reconstructed set of statistical models, which couples together the statistical model parameters of only those L FETs that affect the performance target. Thus, in this reconstructed set, the partial correlations between the statistical model parameters of the L FETs are preserved; however, any correlations between the statistical model parameters of the L FETs and the statistical model parameters of the rest of the FETs (i.e., the FETs that do not affect the performance target) are uncoupled.

For example, an exemplary integrated circuit may comprise four different types of field effect transistors (i.e., K=4) including a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), and a regular threshold voltage p-type field effect transistor (RVT pFET). Eqs. (18a)-(18d) above illustrate the full set of four statistical models for the four different types of FETs in this integrated circuit, when only a single type of statistical model parameter, namely, channel length, is considered. Typically, in this case, the total number M of additional simulations required for corner model generation would be equal to the total number N of corresponding statistical model parameters, which would be equal to KJ=4×1=4. However, if a determination is made that in this integrated circuit a lesser number L (e.g., only RVT nFET and RVT pFET) of the total number K of the different types of field effect transistors are known to affect the performance target (e.g., delay of an inverter), then the additional simulation runs at process 904 can be focused only on this pair of transistors, RVT nFET and RVT pFET and the number M of additional simulation runs will be equal to I, which is equal to the product of J and L. However, in order to accomplish this, the full set of four statistical models as shown in Eqs. (18a)-(18d), which couples the four corresponding statistical model parameters and, particularly, the four channel lengths of the four different types of FETs together, must be reconstructed into a smaller, reconstructed set of statistical models as shown in Eqs. (38a)-(38b) below, which couples together the statistical model parameters and, particularly, the channel lengths of only the RVT nFET and RVT pFET that affect the performance target.

After reconstructing the full set of statistical models into the smaller, reconstructed set of statistical models (38a) and (38b), the initial simulation run for the corner model can be performed at process 902, as discussed above, to determine a nominal delay value (τ_(nom)). Then, at process 904, only two additional simulation runs need to be performed with the channel lengths of RVT nFET and RVT pFET set, using the reconstructed set of statistical models of Eqs. (38a) and (38b), at different channel length values that are offset from their respective nominal channel length values in correlated ways. Specifically, for the first additional simulation run, the channel lengths (C_(rvtn) and L_(rvtp)) of only the transistors RVT nFET and RVT pFET can be set such that they are offset along the g₁ direction (see Eqs. (39a)-(39b)). Based on the results of the first additional simulation run, a first corner performance value τ₁ can be obtained. For a second additional simulation run, the channel lengths (L_(rvtn) and L_(rvtp)) of only the transistors RVT nFET and RVT pFET can be set such that they are offset along the g₂ direction (see Eqs. (40a)-(40b)). Based on the results of the second additional simulation run, a second corner performance value τ₂ can be obtained.

After obtaining nominal performance value τ_(nom) and two corner performance values τ₁ and τ₂, Eqs. (1a)-(1b) can further be used at process 906 to obtain the variance (σ_(τ,corner) ²) and the standard deviation (σ_(τ,corner)) of the performance target (τ).

Also disclosed herein are embodiments of a computer program product. This computer program product can comprise a computer readable storage medium, which stores computer program code. The computer program code can be executable by a computer to perform the above-described method. More specifically, as will be appreciated by one skilled in the art, aspects of the disclosed techniques for generating a field effect transistor (FET) corner model for a given performance target (e.g., delay) can be embodied as a method, system or computer program product. Accordingly, aspects of these techniques may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the disclosed techniques may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable storage device or a computer readable signal medium. A computer readable storage medium is a tangible medium and may be, but is not limited to, any of the following: an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include, but is not limited to, the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage device may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

As mentioned above, the computer readable medium can alternatively comprise a computer readable signal medium that includes a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. This computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the disclosed embodiments may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the disclosed method, system and computer program product are described above with reference to flowchart illustrations and/or block diagrams. It should be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks. The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

FIG. 3 is representative hardware environment for implementing the above-disclosed system, method and/or computer program product. This schematic drawing illustrates a hardware configuration of a computerized device, such as an information handling/computer system. The computerized device comprises at least one processor or central processing unit (CPU) 10. The CPUs 10 are interconnected via bus 12 to various devices such as a random access memory (RAM) 14, read-only memory (ROM) 16, and an input/output (I/O) adapter 18. The I/O adapter 18 can connect to peripheral devices, such as disk units 11 and tape drives 13, or other program storage devices that are readable by the computerized device. The computerized device can read the inventive instructions on the program storage devices and follow these instructions to execute the methodology of the disclosed embodiments. The computerized device further includes a user interface adapter 19 that connects a keyboard 15, mouse 17, speaker 24, microphone 22, and/or other user interface devices such as a touch screen device (not shown) to the bus 12 to gather user input. Additionally, a communication adapter 20 connects the bus 12 to a data processing network 25, and a display adapter 21 connects the bus 12 to a display device 23 which may be embodied as an output device such as a monitor, printer, or transmitter, for example.

It should be noted that the terminology used herein is for the purpose of describing the system, method and computer program product and is not intended to be limiting. For example, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises” “comprising”, “includes” and/or “including”, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Additionally, it should be understood that the corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Disclosed above are a system, method and computer program product for generating a field effect transistor (FET) corner model for a given performance target (e.g., delay) that accurately preserves partial correlations between corresponding statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value (e.g., a nominal delay value) with all field effect transistors set at their nominal model parameter values (e.g., nominal channel length values, nominal threshold voltage values, nominal overlap capacitances, nominal channel lengths, etc.). Then, multiple additional simulation runs are performed to determine corner performance values (e.g., corner delay values). In each successive additional simulation run, the statistical model parameters of the different types of field effect transistors are properly set at different model parameters values (e.g., different channel length values, different threshold voltage values, different overlap capacitance values, different channel width values, etc.) that are offset from their nominal model parameter values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined. This technique preserves the partial correlations between the statistical model parameters of the different types of field effect transistors and does so without requiring the performance of a large number of simulations and without requiring knowledge of the sensitivities of the performance target. 

What is claimed is:
 1. A computer system comprising: a memory storing a design for an integrated circuit comprising at least two different types of field effect transistors; and at least one processor accessing said design in said memory and generating a corner model for a performance target that preserves partial correlations between corresponding statistical model parameter values of said at least two different types field effect transistors by performing the following: performing an initial simulation run to determine a nominal performance value, said corresponding statistical model parameter values of said at least two different types of field effect transistors being set, during said initial simulation run, at nominal model parameter values for said at least two different types of field effect transistors, said at least two different types of field effect transistors comprising at least a first field effect transistor having a first nominal model parameter value and a second field effect transistor having a second nominal model parameter value; performing multiple additional simulation runs to determine corner performance values, said corresponding statistical model parameter values of said at least two different types of field effect transistors being set, during each successive additional simulation run, at different predetermined statistical model parameter values for said at least two different types of field effect transistors that are offset from said nominal model parameters values for said at least two different types of field effect transistors such that, during each successive additional simulation run, a first predetermined statistical model parameter value for said first field effect transistor is offset from said first nominal model parameter value of said first field effect transistor and a second predetermined statistical model parameter value for said second field effect transistor is offset from said second nominal model parameter value of said second field effect transistor; and determining a standard deviation for said performance target based on performance differences between each of said corner performance values and said nominal performance value.
 2. The system of claim 1, said corresponding statistical model parameter values comprising any of channel length values, threshold voltage values, overlap capacitance values and channel width values.
 3. The system of claim 1, said performance target comprising delay.
 4. The system of claim 1, said determining of said standard deviation comprising solving a root sum of squares expression.
 5. The system of claim 1, said performing of said multiple additional simulation runs comprising, for each additional simulation run, setting said first predetermined statistical model parameter value for said first field effect transistor equal to said first nominal model parameter value for said first field effect transistor plus a first specific multiple of a standard deviation and setting said second predetermined statistical model parameter value for said second field effect transistor equal to said second nominal model parameter value for said second field effect transistor plus a second specific multiple of said standard deviation.
 6. The system of claim 5, said first specific multiple and said second specific multiple comprising multiples associated with random variables representative of said partial correlations within a set of statistical models.
 7. The system of claim 5, said first specific multiple and said second specific multiple each being between −3 and
 3. 8. The system of claim 1, said at least two different types of field effect transistors comprising a total number K of different types of field effect transistors, said multiple additional simulation runs comprising a total number M of additional simulation runs, where said total number M is no greater than a product of said total number K of different types of field effect transistors and a number J of different types of statistical model parameters under consideration for each of said different types of field effect transistors.
 9. A method comprising: accessing, from a memory by a computer system, a design for an integrated circuit comprising at least two different types of field effect transistors; and generating, by said computer, a corner model for a performance target that preserves partial correlations between corresponding statistical model parameter values of said at least two different types of field effect transistors, said generating comprising: performing, by said computer system, an initial simulation run to determine a nominal performance value, said corresponding statistical model parameter values of said at least two different types of field effect transistors being set, during said initial simulation run, at nominal model parameter values for said at least two different types of field effect transistors, said at least two different types of field effect transistors comprising at least a first field effect transistor having a first nominal model parameter value and a second field effect transistor having a second nominal model parameter value; performing, by said computer system, multiple additional simulation runs to determine corner performance values, said corresponding statistical model parameter values of said at least two different types of field effect transistors being set, during each successive additional simulation run, at different predetermined statistical model parameter values for said at least two different types of field effect transistors that are offset from said nominal model parameters values for said at least two different types of field effect transistors such that, during each successive additional simulation run, a first predetermined statistical model parameter value for said first field effect transistor is offset from said first nominal model parameter value of said first field effect transistor and a second predetermined statistical model parameter value for said second field effect transistor is offset from said second nominal model parameter value of said second field effect transistor; and, determining, by said computer system, a standard deviation for said performance target based on performance differences between each of said corner performance values and said nominal performance value.
 10. The method of claim 9, said corresponding statistical model parameter values comprising any of channel length values, threshold voltage values, overlap capacitance values and channel width values.
 11. The method of claim 9, said performance target comprising delay.
 12. The method of claim 9, said determining of said standard deviation comprising solving a root sum of squares expression.
 13. The method of claim 9, said performing of said multiple additional simulation runs comprising, for each additional simulation run, setting said first predetermined statistical model parameter value for said first field effect transistor equal to said first nominal model parameter value for said first field effect transistor plus a first specific multiple of a standard deviation and setting said second predetermined statistical model parameter value for said second field effect transistor equal to said second nominal model parameter value for said second field effect transistor plus a second specific multiple of said standard deviation.
 14. The method of claim 13, said first specific multiple and said second specific multiple comprising multiples associated with random variables representative of said partial correlations within a set of statistical models.
 15. The method of claim 13, said first specific multiple and said second specific multiple each being between −3 and
 3. 16. The method of claim 9, said at least two different types of field effect transistors comprising a total number K of different types of field effect transistors, said multiple additional simulation runs comprising a total number M of additional simulation runs, where said total number M is no greater than a product of said total number K of different types of field effect transistors and a number J of different types of statistical model parameters under consideration for each of said different types of field effect transistors.
 17. A computer program product comprising a computer readable storage device storing computer program code, said computer program code being executable by a computer to perform a method, said method comprising: accessing a design for an integrated circuit comprising at least two different types of field effect transistors; and generating a corner model for a performance target that preserves partial correlations between corresponding statistical model parameter values of said at least two different types of field effect transistors, said generating comprising: performing an initial simulation run to determine a nominal performance value, said corresponding statistical model parameter values of said at least two different types of field effect transistors being set, during said initial simulation run, at nominal model parameter values for said at least two different types of field effect transistors, said at least two different types of field effect transistors comprising at least a first field effect transistor having a first nominal model parameter value and a second field effect transistor having a second nominal model parameter value; performing multiple additional simulation runs to determine corner performance values, said corresponding statistical model parameter values of said at least two different types of field effect transistors being set, during each successive additional simulation run, at different predetermined statistical model parameter values for said at least two different types of field effect transistors that are offset from said nominal model parameters values for said at least two different types of field effect transistors such that, during each successive additional simulation run, a first predetermined statistical model parameter value for said first field effect transistor is offset from said first nominal model parameter value of said first field effect transistor and a second predetermined statistical model parameter value for said second field effect transistor is offset from said second nominal model parameter value of said second field effect transistor; and determining a standard deviation for said performance target based on performance differences between each of said corner performance values and said nominal performance value.
 18. The computer program product of claim 17, said corresponding statistical model parameter values comprising any of channel length values, threshold voltage values, overlap capacitance values and channel width values, and said performance target comprising delay.
 19. The computer program product of claim 17, said determining of said standard deviation comprising solving a root sum of squares expression.
 20. The computer program product of claim 17, said performing of said multiple additional simulation runs comprising, for each additional simulation run, setting said first predetermined statistical model parameter value for said first field effect transistor equal to said first nominal model parameter value for said first field effect transistor plus a first specific multiple of a standard deviation and setting said second predetermined statistical model parameter value for said second field effect transistor equal to said second nominal model parameter value for said second field effect transistor plus a second specific multiple of said standard deviation, and said first specific multiple and said second specific multiple comprising multiples associated with random variables representative of said partial correlations within a set of statistical models. 